RTL Design Engineer

Job Type: Full Time

Work Mode: WFO

Exp: N/A

Qualification: B. Tech/B.E/M.Tech

Skill Required: RTL design, Lint, CDC, spyglass, Microarchitecture design, VHDL

Location: Bangalore

Job description:

• Proficiency in RTL designs using Verilog/SystemVerilog/VHDL based on specifications.
• Solid understanding of digital design concepts, including pipelining, clock domain crossing (CDC), and reset strategies.
• Experience with industry-standard tools for synthesis, linting, and STA (e.g., Synopsys Design Compiler, Mentor Questa, or Cadence Genus).
• Collaborate with system architects to understand requirements and translate them into micro-architectures.
• Perform design optimization for performance, power, and area (PPA).
• Work with verification teams to define test plans and debug issues in simulations and emulation environments.
• Address synthesis, timing, and functional issues through RTL modifications.
• Create and maintain design specifications, architecture diagrams, and documentation for IP or SoC blocks.
• Provide support for integration and bring-up activities.”