Job Type: Full Time
Work Mode: WFO
Exp: 5-12 Years
Qualification: B. Tech/B.E/M.Tech
Location: Bangalore
Skills Required: GLS, Gate level simulation, System verilog
Job description:
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
- 5 to 12 years of relevant industry experience in IP and SoC verification.
- Strong expertise in SystemVerilog (SV) and Universal Verification Methodology (UVM).
- Proficiency in Gate-Level Simulation (GLS).
- Good knowledge of AMBA standards (OCP, AXI, AHB, APB).
- Experience with scripting and SystemVerilog Assertions (SVA).
Preferred Skills:
- Experience with coverage-driven constrained random validation.
- Familiarity with OOP concepts and verification methodologies like UVM and OVM.
- Strong problem-solving skills and attention to detail.